When several semiconductor devices are provided on a chip, it is required to isolate them from each other in order to suppress parasitic capacitances. Shallow trench isolation is known, whereby trenches are etched into the surface of the semiconductor layer structure in which the devices are formed. However, for high performance bipolar applications, shallow trench isolation is not sufficient to suppress parasitic capacitances. To improve the isolation characteristics, the integration of deep trenches in addition to shallow trench isolation is required in structures formed on silicon on insulator substrates. This is especially beneficial, but not limited to cases where the structures are formed on silicon on insulator substrates. The same applies where the structures are formed from bulk silicon.
Integrated sequences for combined deep and shallow trench isolation have been disclosed in which the deep trench is formed first and then filled with a resist plug, upon which shallow trenches are subsequently patterned. However, the known methods of forming integrated deep and shallow trench isolation structures are not suitable for very deep trenches. This is because either the number of deep trenches per unit area or the depth of the deep trenches needs to be limited, in order to avoid insufficient filling with resist before the shallow trench pattern is formed.